Freescale Semiconductor /MKV58F24 /SystemControl /CM7_CACR

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Interpret as CM7_CACR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)SIWT 0 (0)ECCDIS 0 (0)FORCEWT

SIWT=0, ECCDIS=0, FORCEWT=0

Description

L1 Cache Control Register

Fields

SIWT

Shared cacheable-is-WT for data cache. Enables limited cache coherency usage.

0 (0): Normal Cacheable Shared locations are treated as being Non-cacheable. Default mode of operation for Shared memory.

1 (1): Normal Cacheable shared locations are treated as Write-Through.

ECCDIS

Enables ECC in the instruction and data cache.

0 (0): Enables ECC in the instruction and data cache.

1 (1): Disables ECC in the instruction and data cache.

FORCEWT

Enables Force Write-Through in the data cache.

0 (0): Disables Force Write-Through.

1 (1): Enables Force Write-Through. All Cacheable memory regions are treated as Write-Through.

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